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Solid-State Circuits, IEEE Journal of
Top Documents Accessed: Mar 2009
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Article Information
1.
A New Transceiver Architecture for the 60-GHz Band
Parsa, A.; Razavi, B.
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 751-762
Digital Object Identifier 10.1109/JSSC.2008.2012368

Abstract | Full Text: PDF (1404 KB) (1404 KB)

2.
Multi-Standard Mobile Broadcast Receiver LNA With Integrated Selectivity and Novel Wideband Impedance Matching Technique
Tae Wook Kim; Muthali, H.; Sengupta, S.; Barnett, K.; Jaffee, J.
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 675-685
Digital Object Identifier 10.1109/JSSC.2008.2011035

Abstract | Full Text: PDF (1204 KB) (1204 KB)

3.
A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner
Donggu Im; Ilku Nam; Hong-Teuk Kim; Kwyro Lee
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 686-698
Digital Object Identifier 10.1109/JSSC.2008.2010804

Abstract | Full Text: PDF (959 KB) (959 KB)

4.
A Low-Power, Linearized, Ultra-Wideband LNA Design Technique
Heng Zhang; Xiaohua Fan; Sinencio, E.S.
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 2, Date: Feb. 2009, Pages: 320-330
Digital Object Identifier 10.1109/JSSC.2008.2011033

Abstract | Full Text: PDF (711 KB) (711 KB)

5.
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques
Temporiti, E.; Weltin-Wu, C.; Baldi, D.; Tonietto, R.; Svelto, F.
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 824-834
Digital Object Identifier 10.1109/JSSC.2008.2012363

Abstract | Full Text: PDF (1971 KB) (1971 KB)

6.
A 2.4–2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters
Shanaapos;a, O.
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 699-707
Digital Object Identifier 10.1109/JSSC.2008.2010975

Abstract | Full Text: PDF (503 KB) (503 KB)

7.
A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp
Byung-Geun Lee; Tsang, R.M.
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 883-890
Digital Object Identifier 10.1109/JSSC.2009.2013761

Abstract | Full Text: PDF (697 KB) (697 KB)

8.
A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13$ mu$m CMOS
Zhiheng Cao; Shouli Yan; Yunchu Li
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 862-873
Digital Object Identifier 10.1109/JSSC.2008.2012329

Abstract | Full Text: PDF (2093 KB) (2093 KB)

9.
A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 $mu$ m CMOS
Ming-Ching Kuo; Shiau-Wen Kao; Chih-Hung Chen; Tsung-Shuen Hung; Yi-Shing Shih; Tzu-Yi Yang; Chien-Nan Kuo
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 740-750
Digital Object Identifier 10.1109/JSSC.2008.2012366

Abstract | Full Text: PDF (2666 KB) (2666 KB)

10.
A Single–Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and ${+}$90 dBm IIP2
Kaczman, D.; Shah, M.; Alam, M.; Rachedine, M.; Cashen, D.; Lu Han; Raghavan, A.
Solid-State Circuits, IEEE Journal of
Volume 44, Issue 3, Date: March 2009, Pages: 718-739
Digital Object Identifier 10.1109/JSSC.2009.2013762

Abstract | Full Text: PDF (2066 KB) (2066 KB)

 
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