This paper describes design techniques to maximize the efficiency and power density of fully integrated switched-capacitor (SC) DC-DC converters. Circuit design methods are proposed to enable simplified gate drivers while supporting multiple topologies (and hence output voltages). These methods are verified by a proof-of-concept converter prototype implemented in 0.374 mm² of a 32 nm SOI process. The 32-phase interleaved converter can be configured into three topologies to support out... Read More »

Millimeter-wave transmitters designed for dense signal constellations must deal with severe linearity-efficiency trade-offs. This paper proposes a method of blending beamforming and linearization that reduces the number of power amplifiers and avoids the loss of on-chip transformers. Two constant-envelope beams are combined in space to deliver a variable-envelope signal, relaxing the linearity of transmitters. A dual-transmitter prototype fabricated in 65-nm CMOS technology and designed for the ... Read More »

A 4-port-inductor-based voltage-controlled oscillator (VCO) coupling technique is introduced to improve VCO phase noise performance. The analysis of the stability of oscillation modes and the phase noise performance of a coupled oscillator is provided as theoretical fundamental. Four-port inductors are compared with typical two-port inductors, and their superior performance over the latter is demonstrated through analysis and measurements. The design strategies of coupled VCOs using 4-port induc... Read More »

A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances th... Read More »

A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking; and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The proposed proportional path decouples the detector quantization error and oscillator noise bandwidth tradeoff and helps maximize bandwidth to suppress digitally controlled oscillator (DCO) phase noise in a power efficient manner. A double integral path a... Read More »

This paper presents a technique to efficiently supply power over a wide power range using a fully-integrated on-chip converter for dynamic voltage scaling (DVS) based applications. All components, including filter elements, are integrated on-chip. To achieve high efficiency the converter adaptively switches between different modes of operation by detecting the output current. The design, implemented in IBM 130 nm CMOS technology, achieves a peak efficiency of 77% at reduced temperature of 8&#x00... Read More »

A 10-b, 100-MS/s pipelined analog-to-digital converter (ADC) without dedicated front-end sample-and-hold amplifier (SHA) converts from dc to the 12th Nyquist band with in situ, mostly digital background calibration for the clock skew in the 3.5-b front-end stage. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the front-end sub-ADC to synchronize with th... Read More »

A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-GHz switching Inverse Class-D power amplifier. Low-power digital filtering on the amplitude path helps remove spectral images for coexistence. The transmitter integrates the complete LO distribution network and digital drivers. Operating from a 1-V supply, the PA has 21.8-dBm peak output power with 44% efficiency. Simple static predistortion helps the transmitter meet EVM and mask requirements of 802.11g... Read More »

This paper analyzes various aspects of the performance of LC VCOs over temperature with emphasis on the temperature dependence of K_VCO. A novel frequency-tuning scheme is proposed which allows wide temperature range operation while keeping the average K_VCO low. Read More »

This paper presents an efficient energy harvester for RF-powered sensor networks. The circuit is based on an improved multi-stage rectifier, which exploits a fully passive threshold self-compensation scheme to overcome the limitation due to the input dead zone. A CAD-oriented design methodology is also proposed, which is aimed at maximizing the overall power conversion efficiency of the harvester through an optimum trade-off among matching losses, power reflection and rectifier efficiency. Accor... Read More »

The linearity of conventional active-RC filters is limited by the operational transconductance amplifiers (OTAs) used in the integrators. Transconductance-capacitance (Gm-C) filters are fast and can be linear- however, they are sensitive to parasitic capacitances. We explore the Gm-assisted OTA-RC technique, which is a way of combining Gm-C and active-RC integrators in a manner that enhances the linearity and speed of the latter, while adding negligible extra noise or power dissipation. Measurem... Read More »

A new enhanced swing differential Colpitts VCO architecture enables oscillations to go beyond both the supply voltage and ground making it suitable for low voltage operation. Analysis for the oscillation frequency, differential- and common-mode oscillations, amplitude of oscillation, and start-up condition provides insight into oscillator operation and design considerations. Operating at 4.9 GHz, the VCO consumes from 1.9 mW to 3 mW for supply voltages of 400 mV and 500 mV, respectively. The 130... Read More »

Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar-derived two-stage architecture. Alternative circuit approaches for optimization of particular perfo... Read More »

A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital ... Read More »

A unified receiver front-end (RFE) for mobile TV covering the VHF-III, UHF and L bands is described. Performance, power and area efficiencies are advanced in threefold: 1) a gain-boosting current-balancing balun-LNA exhibits high linearity, wideband output balancing and adequate S₁₁ against gain control; 2) a current-reuse mixer-low-pass-filter merges quadrature-/harmonic-rejection mixing and third-order current-mode post-filtering in one block, enhancing linearity and noise just wher... Read More »

This paper presents an asynchronous SAR ADC for flexible, low energy radios. To achieve excellent power efficiency for a relatively moderate resolution, various techniques are introduced to reduce the power consumption: custom-designed 0.5 fF unit capacitors minimize the analog power consumption while asynchronous dynamic logic minimizes the digital power consumption. The variability of the custom-designed capacitors is estimated by a specialized CAD tool and verified by chip measurements. An im... Read More »

A continuous-time multiple-input multiple-output crosstalk cancellation (MIMO-XTC) architecture operating at 2-6 Gb/s has been proposed. The performance of the XTC equalizer has been measured with various spacings of FR4 channels and data rates. The crosstalk energy reutilization technique efficiently handles crosstalk and achieves high signal integrity in severe crosstalk environments where crosstalk had completely closed the data eye. Measurement results show improvement in jitter... Read More »

This paper reports a digital phase locked loop (D-PLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed converter achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or voltage conversion range. The D-PLL is programmable over a wide range of parameters and can be synchronized to a clock reference to ensure proper frequency lock and switching operation ... Read More »

This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, base... Read More »

This paper presents a multi-MHz buck regulator for portable applications using an auto-selectable peak- and valley-current control (ASPVCC) scheme. The proposed ASPVCC scheme can enable the current-mode buck regulator to reduce the settling-time requirement of the current sensing by two times. In addition, the dynamically biased shunt feedback technique is employed to improve the sensing speed and the sensing accuracy of both the peak and valley current sensors. With both ASPVCC scheme and advan... Read More »

A MOS-input operational amplifier has a reconfigurable input stage that enables trimming of both offset and offset drift based only on single-temperature measurements. The input stage consists of a MOS differential pair, whose offset drift is predicted from offset voltage measurements made at well-defined bias currents. A theoretical motivation for this approach is presented and validated experimentally by characterizing the offset of pairs of discrete MOS transistors as a function of bias curre... Read More »

The integration of photodetectors for optical communication into standard nanoscale CMOS process technologies can enable low cost for emerging high volume short-reach parallel optical communication. Whereas past work has highlighted the challenges that face integrated photodetectors in highly scaled CMOS technologies, this work examines the opportunities afforded by these new technologies. First, scaling promises improved extrinsic photodetector bandwidth thanks to improved TIA performance. Seco... Read More »

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting an 802.15.3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced tones from 43.2 GHz to 51.84 GHz, which is suitable for a heterodyne architecture with F_LO=(4/5)×F_TRX. Phase noise is measured directly at the F_LO frequency and is better than -97.5 dBc/Hz@1 MHz across the entire band. The reported frequency synthesizer is smaller, exhibits less phase noise... Read More »

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which... Read More »

Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex. We pro pose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC. The prototype 12b 50 MS/s ADC achieves an ENOB of 10.4b at Nyquist,... Read More »