IEEE Journal of Solid-State Circuits

This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed b... View full abstract»

This work presents a receiver capable of receiving three simultaneous cellular channels with an aggregate bandwidth of 60 MHz, enabling a 300 Mb/s downlink rate. The receiver has 16 RF LNA ports covering the cellular bands within the 572-2700 MHz frequency range. It supports LTE-advanced Rel-12 Cat6, HSPA+ Rel-11, TD-SCDMA Rel-9, and GSM/EDGE Rel-9. The 40 nm CMOS receiver consumes 13.7 and 17.6 m... View full abstract»

A multimode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency (f₈) and provides a ΔΣ modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around f₈/4, f₈/2, or 3f₈/4. The on-chip 14 ... View full abstract»

A monolithic microwatt-level charge pump energy harvester is proposed for smart nodes of Internet of Things (IOT) networks. Due to the variation of the available voltage and power in IOT scenarios, the charge pump was optimized by the proposed architecture and circuit level innovations. First, a reconfigurable charge pump is introduced to provide the hybrid conversion ratios (CRs) as 1[1/3]×... View full abstract»

We present a highly configurable, low-power, low-area, low-EVM, SAW-less transmitter (TX) architecture that is based on a dynamically biased power mixer. All FDD/TDD bands from 0.7 to 2.7 GHz for 4G LTE Rel-11 and 3G HSPA+ are supported in addition to 2G quad bands. The power-mixer bias current is dynamically adjusted based on the instantaneous baseband signal swing using a fully-differential hybr... View full abstract»

Carrier aggregation is a key feature of the 3GPP LTE-Advanced cellular network standard that combines multiple channels to support higher data rates and improve the utilization of fragmented spectrum holdings. This work presents a cellular transmitter capable of transmitting a maximum of four channels simultaneously, two contiguous channels in two bands, with an aggregate bandwidth of up to 80 MHz... View full abstract»

We propose a switched-capacitor radio-frequency (RF) front end achieving an equivalent high-order, tunable, highly linear RF filtering to improve the out-of-band (OB) blocker tolerance. RF input impedance matching, N-path filtering, high-order discrete-time infinite-impulse response (IIR) filtering, and down-conversion are implemented using only switches and capacitors in a 0.1-0.7 GHz prototype w... View full abstract»

This paper presents a fully integrated 60 GHz directconversion transceiver in 45 nm SOI CMOS for same-channel full-duplex (FD) wireless communication. FD operation is enabled by a novel polarization-based wideband reconfigurable selfinterference cancellation (SIC) technique in the antenna domain. The antenna cancellation can be reconfigured from the IC to combat the variable SI scattering from the... View full abstract»

This paper presents an 11 bit 450 MS/s three-way time-interleaved (TI) subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC). The proposed hybrid architecture combines the design benefits of different ADC structures to achieve a high conversion rate and accuracy with good power efficiency. The design employs multiple offset calibration schemes to compensate... View full abstract»

This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5-13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5 tap DFE, and fully digital CDR followed ... View full abstract»

Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architect... View full abstract»

This paper presents an all-digital class-G quadrature switched-capacitor power amplifier (Q-SCPA) implemented in 65 nm CMOS. It combines in-phase (I) and quadrature (Q) signals on a shared capacitor array. The I/Q signals are digitally weighted and combined in the charge domain. Quadrature summation results in a 3 dB signal loss; Hence the Q-SCPA utilizes a class-G dual-supply architecture to impr... View full abstract»

This paper presents a 28 Gb/s multistandard SerDes macro which is fabricated in TSMC 28 nm CMOS process. The transimpedance amplifier (TIA) base analog front-end achieved 15 dB high-frequency boost with an on-chip compact passive inductor. The adaptation loop for the boost is decoupled from the decision feedback equalizer (DFE) adaptation by the use of a group delay algorithm. The DFE is a half-ra... View full abstract»

This paper presents a digital bang-bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the automatic loop gain control techn... View full abstract»

The high phase noise of ring oscillators has generally discouraged their use in RF synthesis. This paper introduces an integer-N synthesizer that employs a type-I loop to achieve a wide bandwidth, allowing the use of ring oscillators, and a master-slave sampling loop filter along with harmonic traps to suppress spurs. A 2.4 GHz prototype fabricated in 45 nm digital CMOS technology provides a loop ... View full abstract»

The linearity of the vast majority of the ADC topologies is limited by the linearity of the circuit elements employed in their design, such as resistors and capacitors. This paper presents a charge-mode SAR ADC architecture that uses only highly nonlinear metal-oxide-semiconductor capacitors (MOSCAPs) as the DAC capacitance elements. The non-linearity of the MOSCAPs is exploited to improve the tol... View full abstract»

Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has al... View full abstract»

The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An ... View full abstract»

This paper presents a 10 nW-1 μW power management IC with 3.2 nW quiescent power consumption for solar energy harvesting applications. The chip integrates a switch matrix that can be configured as a buck or a boost dc-dc converter using a single inductor as well as output voltage regulation logic, battery management block, and self-startup. The control circuit of the converter is designed i... View full abstract»

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually... View full abstract»

This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a single-amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two amplifiers are needed for... View full abstract»

A three-stage Greinacher rectifier is designed using ultra-low-leakage CMOS diodes and characterized at 13.56 MHz for a 1 Vpp sinusoidal input and a 10 μA load current in 250 nm CMOS bulk technology. The measured dc output voltage is 1.9 V with 72% power conversion efficiency providing a 19 μW output power. This ultra-low-power and high-efficiency ac/dc power converter with 0.13 mm View full abstract»

An 80 GHz transmitter leakage cancellation circuit is implemented and integrated together with a low-noise amplifier (LNA) as part of a receiver front-end for a phase-modulated continuous-wave radar. The cancellation is achieved by subtracting a copy of the leakage signal from the received one at the output of the LNA. The system incorporates an analog feedback loop to adjust the amplitude of the ... View full abstract»

Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar... View full abstract»

A digitally intensive transmitter using RF pulsewidth-modulation (PWM) with a class-D power amplifier (PA) is described. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs full carrier frequency for half of the amplitude range and the second harmonic of half of the carrier frequency,... View full abstract»

This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high d... View full abstract»

We introduce a 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P5M CMOS process, suitable for use in Microsoft Kinect for XBOX ONE. The 10 μm × 10 μm pixel incorporates a TOF detector that operates using the quantum efficiency modulation (QEM) technique at high modulation frequencies of up to 130 MHz, achieves a modulation contras... View full abstract»

A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic de... View full abstract»

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V_ref is the sum of the built-in voltage of the diode V_f and the thermal voltage V_T of kT/q multiplied by a constant. Therefore, V_ref is about 1.25 V, which limits a low supply-voltage operatio... View full abstract»

Multichannel neural amplifiers are commonly implemented with a shared reference whose input impedance is several times lower than that of the corresponding signal inputs. This huge impedance mismatch significantly degrades the total common mode rejection ratio (TCMRR) regardless of the amplifier's intrinsic CMRR (ICMRR). This study reports a multichannel neural amplifier system that eliminates thi... View full abstract»

Linear time-invariant (LTI) phase noise theories provide important qualitative design insights but are limited in their quantitative predictive power. Part of the difficulty is that device noise undergoes multiple frequency translations to become oscillator phase noise. A quantitative understanding of this process requires abandoning the principle of time invariance assumed in most older theories ... View full abstract»

An ultra low-energy oscillator circuit is presented for use in picowatt level systems. The core oscillator uses an 18 transistor 3 stage architecture designed to minimize short circuit current. In addition, a transistor threshold is used to set the trip point as opposed to a voltage reference and comparator scheme, leading to overall energy savings. While operating across a wide range of low frequ... View full abstract»

A 0.13 μm CMOS system on a chip (SoC) for 64 channel neuroelectrical monitoring and responsive neurostimulation is presented. The direct-coupled chopper-stabilized neural recording front end rejects up to ±50 mV input dc offset using an in-channel digitally assisted feedback loop. It yields a compact 0.018 mm² integration area and 4.2 μVrms integrated input-referred... View full abstract»

We propose an ADC-digital codesign approach to IF sampling digital beamforming (DBF) that combines continuous-time bandpass ΔΣ modulators (CTBPDSMs) and bit-stream processing (BSP). This approach enables power-and area-efficient DBF by removing the need for digital multipliers and multiple decimators. The prototype beamformer digitizes eight 260 MHz IF signals at 1040 MS/s with eight... View full abstract»

The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several b... View full abstract»

A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of concern and enables a tradeoff between different architectures with respect to the analog input bandwidth, the hold time of the sampled signal, a... View full abstract»

A dual time-constant rail clamp for protecting CMOS circuits during electrostatic discharge (ESD) events is described. In the new circuit, a relatively small time constant is dynamically adjusted after the clamp is triggered during the ESD event, to keep the clamp conducting and dissipate the full ESD energy. The design is area-efficient, can support applications with power-on times as fast as 200... View full abstract»

CANCER is a reasonably general circuit analysis program especially suited to integrated-circuit simulation. The program provides for the analysis of large circuits in the following four modes of operation: nonlinear d.c., large-signal transient, small-signal a.c., and thermal and shot noise. These subanalysis capabilities are intercoupled appropriately for convenience and efficiency. Internally, C... View full abstract»

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing funct... View full abstract»

While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital equalization for high data rate operation, the ADC and digital equalization power consumption is a key concern in applications that support operation over a wide range of channels with varying amounts of intersymbol interference (ISI). This paper presents a hybrid ADC-based receiver architecture which emplo... View full abstract»

A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of... View full abstract»

The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation f... View full abstract»

This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filte... View full abstract»

A pulsed ultrawideband (UWB) transceiver with four-element receiver beamforming is described. Multiband signaling with frequency hopping is employed to efficiently utilize spectrum from 6 to 8.5 GHz to achieve a high data rate of 1 Gbps. A pulse-based signaling approach with low implementation complexity is utilized. Frequency-hopping reduces the overhead for multiband implementation by sharing mu... View full abstract»

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid ... View full abstract»

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier... View full abstract»

Efforts towards energy-harvesting solutions are targeted for wireless sensor node applications and focus on performing maximum power extraction and storing power, yet efforts to deliver a regulated supply to voltage-sensitive blocks in power-limited applications has yet to be fully achieved. This paper presents a low-power, autonomous power management unit (PMU) able to perform maximum power point... View full abstract»

SRAM cell read stability and write-ability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and V_dd scaling. This paper analyzes the read stability N-curve metrics and compares them with the commonly used static noise margin (SNM) metric defined by Seevinck. Additionally, new write-ability metrics derived from the same N-curve a... View full abstract»

The first feedforward continuous-time ΔΣ ADC with a finite impulse response (FIR) DAC is presented for consumer radio applications. It provides robust loop-delay compensation with no performance degradation in the presence of radio out-of-band blockers from either out-of-band gain peaking in the signal transfer function or blocker clock-jitter modulation. A half-clock-period-delay ha... View full abstract»

Single-bit continuous-time sigma-delta modulators (CTDSMs) are overly sensitive to clock jitter when a non-return-to-zero (NRZ) feedback DAC is used. One way of addressing this problem is to use a DAC with an exponentially decaying pulse shape, realized using a switched capacitor (SC). Existing variants of the SC feedback DAC degrade linearity due to the high peak-to-average ratio of the feedback ... View full abstract»