Analog High Speed Computation
by José Pineda de Gyvez and Edgar Sánchez-Sinencio. This
research deals with the theoretical, practical, and software development of massively
parallel interconnected analog signal processors for high speed computation. This will
allow the modeling of different physical systems such as fluid dynamics or any system
characterized by its spatio-temporal dynamics, including the solution of partial
differential equations on-line, real-time. Key basic hardware building blocks using filed
programmable and current mode techniques will be developed taking into account area,
testability and fault diagnosis, power consumption, and manufacturability issues.
Potential technologies for implementations are CMOS, BiCMOS and GaAs. CAD tools for
behavioral simulation and hardware synthesis will be implemented to deal with image
processing tasks involving a significant number of pixels.
Real-time video processing using Cellular
Neural Networks (CNN) by Ajay Kumar
Kanji and José Pineda de Gyvez. The goal of the research is to construct a video
processing system using cellular neural networks as the core processors. The input and
output signals of the system are NTSC (TV) signals. The system operates using a pipeline
architecture and is briefly described next. The input signal (which comes from a CCD
camera) is converted to a digital representation and stored in a video memory bank. This
memory bank can hold up to four frames of the video image. The CNN processors operate on
the images held in this bank. The processed images are then placed in an output memory
bank and now the result is converted back to analog (NTSC) for display.
Multi-Valued Cellular Neural Networks (MV-CNN)
for Parallel Image Processing by Sam
Villareal and José Pineda de Gyvez. We have developed a set of rules for parallel
processing of black and white images using MV-CNN. Our objectives are to demonstrate the
feasibility of these rules through implementation in 1.2-um CMOS technology and through
simulations of integrated circuits of CMOS devices and Quantum-Well Devices (QWDs). The
parallel processing approach is expected to process larger images more rapidly than binary
CNNs because an image could be processed in fewer loading/processing/unloading iterations.
Furthermore, incorporating QWDs with CMOS circuits has resulted in very compact designs
because of the discrete energy states corresponding to multiple operating points in QWD
current-voltage characteristics.
Field-programmable analog array for signal
processing by Xiaohong Quan and
Sherif Embabi. The ultimate goal of the research in FPAAs is to find generic FPAA
analogous to the digital FPGA counterpart. It offers a short turn around time and cheap
integrated circuit solution. Based on simple current-mode sub-circuits, our proposed
structure allows for operation at high frequencies and low voltage, and can be implemented
in a digital CMOS process. A novel solution to avoid using excessive number of programming
devices in the signal path has been proposed and demonstrated through simulation. It has
already been employed to implement filters using biquad structures. A prototype has
already been implemented in a 1.2m m digital CMOS process.
An integrated signal conditioning circuit
for simultaneous measurement of temperature and strain by
Jinseok Koh and Sherif Embabi. To develop an integrated
conditioning circuit for simultaneous measurement of temperature and strain utilizing only
four wires from the sensor to the conditioning circuit. A high precision-switched
capacitor instrumentation amplifier is the core circuit. A double correlated sampling
technique is used to achieve high power supply rejection, low dc offset and low 1/f noise.
The instrumentation amplifier is designed to resolve a few µV difference at its input.
Electronic devices for the hearing impaired by Alexander H. Reyes and Edgar Sánchez-Sinencio. The research involves the design of three distinct features for hearing aids: Volume Control, Programmable Interface and Noise Reduction System. The Volume Control Receiver detects incoming signals (DTMF tones), and controls the output of the hearing aid in order to provide the desired volume level to the patient. The Programmable Interface Receiver also decodes the signals, and stores apreprogrammed setting that fits the user's pattern of hearing loss based on an audiogram, and chosen individually for every patient in a given situation (i.e., restaurant, noisy street, watching television). These two features have been implemented and tested successfully using 1.2 mm technology. The last feature, Noise Reduction System, will enable potential users to understand speech and sound in noisy environments such as in restaurants, social gatherings, etc. These designs have an immediate application in today's market and their demand will only increase in the future. More important, their application is not only limited to hearing aid devices but to any design that requires a wireless interface. Noise reduction designs have an even broader application field such as in cars, cellular telephones, portable headphones.