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Title
|
Authors
|
Issue |
A 1-V 24-GHz
17.5-mW phase-locked loop in a 0.18-micron CMOS process
|
Ng, A.W.L.; Leung,
G.C.T.; Ka-Chun Kwok; Leung, L.L.K.; Luong, H.C.; |
Jun 06
IEEE
Xplore |
| The design and
analysis of a DLL-based frequency synthesizer for UWB application
|
Tai-Cheng Lee;
Keng-Jan Hsiao; |
Jun 06
IEEE
Xplore |
Low-power
programmable gain CMOS distributed LNA
|
Zhang, F.; Kinget,
P.R.; |
Jun 06
IEEE
Xplore |
| All-digital
delay-locked loop/pulsewidth-control loop with adjustable duty
cycles |
You-Jen Wang;
Shao-Ku Kao; Shen-Iuan Liu; |
Jun 06
IEEE
Xplore |
| A highly linear
and efficient differential CMOS power amplifier with harmonic
control |
Jongchan Kang;
Jehyung Yoon; Kyoungjoon Min; Daekyu Yu; Joongjin Nam; Youngoo Yang;
Bumman Kim |
Jun 06
IEEE
Xplore |
On the amplitude
and phase errors of quadrature LC-tank CMOS oscillators
|
Mazzanti, A.;
Svelto, F.; Andreani, P |
Jun 06
IEEE
Xplore |
| Millimeter-wave
voltage-controlled oscillators in 0.13-micron CMOS technology
|
Changhua Cao; O,
K.K.; |
Jun 06
IEEE
Xplore |
A CMOS
time-to-digital converter with better than 10 ps single-shot
precision |
Jansson, J.-P.;
Mantyniemi, A.; Kostamovaara, J.; |
Jun 06
IEEE Xplore |
| The design and
analysis of a Miller-divider-based clock generator for MBOA-UWB
application |
Tai-Cheng Lee;
Yen-Chuan Huang; |
Jun 06
IEEE
Xplore |
| Baseband and audio
mixed-signal front-end IC for GSM/EDGE applications |
Baggini, B.;
Basedau, P.; Becker, R.; Bode, P.; Burdenski, R.; Esfahani, F.;
Groeneweg, W.; Helfenstein, M.; Lampe, A.; Ryter, R.; Stephan, R.;
|
Jun 06
IEEE
Xplore |
| A 90-nm CMOS
Doherty power amplifier with minimum AM-PM distortion |
Elmala, M.;
Paramesh, J.; Soumyanath, K.; |
Jun 06
IEEE
Xplore |
| Phase and
amplitude pre-emphasis techniques for low-power serial links
|
Buckwalter, J.F.;
Meghelli, M.; Friedman, D.J.; Hajimiri, A.; |
Jun 06
IEEE
Xplore |
| Dynamic power
optimization of active filters with application to zero-IF receivers
|
Ozgun, M.T.;
Tsividis, Y.; Burra, G.; |
Jun 06
IEEE
Xplore |
| A 155.52
mbps-3.125 gbps continuous-rate clock and data recovery circuit
|
Rong-Jyi Yang;
Kuan-Hua Chao; Sy-Chyuan Hwu; Chuan-Kang Liang; Shen-Iuan Liu;
|
Jun 06
IEEE
Xplore |
| A clock generator
with cascaded dynamic frequency counting loops for wide
multiplication range applications |
Tai-Cheng Lee;
Yen-Chuan Huang; |
Jun 06
IEEE
Xplore |
A 75-dB image
rejection IF-input quadrature-sampling SC Sigma-Delta Modulator
|
Kong-Pang Pun;
Wang-Tung Cheng; Chiu-Sing Choy; Cheong-Fat Chan; |
June 06
IEEE
Xplore |
High-speed circuit
designs for transmitters in broadband data links
|
Jri Lee |
MAY 06
IEEE
Xplore |
| Fast acquisition
clock and data recovery circuit with low jitter |
Ruiyuan Zhang; La
Rue, G.S.; |
MAY 06
IEEE
Xplore |
| Design of charge
pump circuit with consideration of gate-oxide reliability in
low-voltage CMOS processes |
Ming-Dou Ker;
Shih-Lun Chen; Chia-Shen Tsai; |
MAY 06
IEEE
Xplore |
| A single-chip
tri-band (2100; 1900; 850/800 MHz) WCDMA/HSDPA cellular transceiver
|
Kaczman, D.L.;
Shah, M.; Godambe, N.; Alam, M.; Guimaraes, H.; Han, L.M.;
Rachedine, M.; Cashen, D.L.; Getka, W.E.; Dozier, C.; Shepherd,
W.P.; Couglar, K.; |
MAY 06
IEEE
Xplore |
| A 0.7-2-GHz
self-calibrated multiphase delay-locked loop |
Hsiang-Hui Chang;
Jung-Yu Chang; Chun-Yi Kuo; Shen-Iuan Liu; |
MAY 06
IEEE
Xplore |
A digitally
controlled oscillator system for SAW-less transmitters in cellular
handsets
|
Chih-Ming Hung;
Staszewski, R.B.; Barton, N.; Meng-Chang Lee; Leipold, D.;
|
MAY 06
IEEE
Xplore |
| Highly linear
0.18-mciron CMOS power amplifier with deep n-Well structure
|
Jongchan Kang;
Daekyu Yu; Youngoo Yang; Bumman Kim; |
MAY 06
IEEE
Xplore |
A 1.5-V multi-mode
quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS
process
|
Bakkaloglu, B.;
Fontaine, P.; Mohieldin, A.N.; Solti Peng; Sher Jiun Fang; Dulger,
F.; |
MAY 06
IEEE
Xplore |
| Self-calibrated
quadrature generator for WLAN multistandard frequency
synthesizer |
Valero-Lopez,
A.Y.; Sung Tae Moon; Sanchez-Sinencio, E.; |
MAY 06
IEEE
Xplore |
Shielded passive
devices for silicon-based monolithic microwave and millimeter-wave
integrated circuits
|
Cheung, T.S.D.;
Long, J.R.; |
MAY 06
IEEE
Xplore |
Analysis of
reliability and power efficiency in cascode class-E PAs
A
quad-band 8PSK/GMSK polar transceiver |
Hietala,
A.W |
MAY 06
IEEE
Xplore |
A new transponder
architecture with on-chip ADC for long-range telemetry applications
|
Kocer, F.; Flynn,
M.P.; |
MAY 06
IEEE
Xplore |
| A 13-dB IIP3 Improved
Low-Power CMOS RF Programmable Gain Amplifier Using Differential
Circuit Transconductance Linearization for Various Terrestrial
Mobile D-TV Applications |
Tae Wook Kim; Bonkee Kim;
|
APR 06
IEEE
Xplore |
| A 20-GHz Phase-Locked Loop for 40-Gb/s Serializing
Transmitter in 0.13-micron CMOS |
Jaeha Kim; Jeong-Kyoum Kim; Bong-Joon Lee; Namhoon Kim;
Deog-Kyoon Jeong; Kim, W.; |
APR 06
IEEE
Xplore |
| A 14-bit Digitally
Self-Calibrated Pipelined ADC With Adaptive Bias Optimization for
Arbitrary Speeds Up to 40 MS/s |
Iizuka, K.; Matsui, H.;
Ueda, M.; Daito, M.; |
APR 06
IEEE
Xplore |
| A CMOS Ultra-Wideband Impulse Radio Transceiver for 1-Mb/s
Data Communications and plus or minus 2.5-cm Range Finding |
Terada, T.; Yoshizumi, S.; Muqsith, M.; Sanada, Y.; Kuroda,
T.; |
APR 06
IEEE
Xplore |
| An Energy-Efficient
Analog Front-End Circuit for a Sub-1-V Digital Hearing Aid Chip
|
Sunyoung Kim; Jae-Youl
Lee; Seong-Jun Song; Namjun Cho; Hoi-Jun Yoo; |
APR 06
IEEE
Xplore |
| A 1-MHZ Bandwidth 3.6-GHz 0.18-micron CMOS Fractional-N
Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced
Broadband Phase Noise |
Meninger, S.E.; Perrott, M.H.; |
APR 06
IEEE
Xplore |
| A Direct Digital
Frequency Synthesizer With Fourth-Order Phase Domain Delta Sigma
Noise Shaper and 12-bit Current-Steering DAC |
Fa Foster Dai; Weining
Ni; Shi Yin; Jaeger, R.C.; |
APR 06
IEEE
Xplore |
| A Multi-Rate 9.953-12.5-GHz 0.2-micron SiGe BiCMOS LC
Oscillator Using a Resistor-Tuned Varactor and a Supply Pushing
Cancellation Circuit |
Maxim, A.; |
APR 06
IEEE
Xplore |
| Introduction to the
Special Issue on the 2005 Symposium on VLSI Circuits |
|
APR 06
IEEE
Xplore |
A CMOS Oversampled DAC With Multi-Bit Semi-Digital
Filtering and Boosted Subcarrier SNR for ADSL Central Office Modems
|
Lin, A.C.Y.; Su, D.K.; Hester, R.K.; Wooley, B.A.; |
APR 06
IEEE
Xplore |
Enhancing Microprocessor
Immunity to Power Supply Noise With Clock-Data Compensation
|
Wong, K.L.; Rahal-Arabi,
T.; Ma, M.; Taylor, G.; |
APR 06
IEEE
Xplore |
|
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline
ADC for a dual-mode 802.11b/Bluetooth receiver |
Bo Xia; Valdes-Garcia, A.; Sanchez-Sinencio, E.; |
Mar 06
IEEE
Xplore |
| A 3-to-8-GHz fast-hopping
frequency synthesizer in 0.18-/spl mu/m CMOS technology |
Jri Lee; |
Mar 06
IEEE
Xplore |
| A +78 dBm IIP2 CMOS direct downconversion mixer for fully
integrated UMTS receivers |
Brandolini, M.; Rossi, P.; Sanzogni, D.; Svelto, F.;
|
Mar 06
IEEE
Xplore |
| Analysis and equalization
of data-dependent jitter |
Buckwalter, J.F.;
Hajimiri, A.; |
Mar 06
IEEE
Xplore |
| Cancellation of crosstalk-induced jitter |
Buckwalter, J.F.; Hajimiri, A.; |
Mar 06
IEEE
Xplore |
| A 56-mW 23-mm2
single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm2
radio |
Gramegna, G.; Mattos,
P.G.; Losi, M.; Das, S.; Franciotta, M.; Bellantone, N.G.; Vaiana,
M.; Mandara, V.; Paparo, M.; |
Mar 06
IEEE
Xplore |
| A comparison of substrate noise coupling in lightly and
heavily doped CMOS processes for 2.4-GHz LNAs |
Hazenboom, S.; Fiez, T.S.; Mayaram, K.; |
Mar 06
IEEE
Xplore |
A CMOS mixed-signal
clock and data recovery circuit for OIF CEI-6G+ backplane
transceiver |
He, M.Y.; Poulton, J.;
|
Mar 06
IEEE
Xplore |
Analysis and design of high-performance asynchronous
sigma-delta Modulators with a binary quantizer |
Ouzounov, S.; Engel Roza; Hegt, J.A.; van der Weide, G.; van
Roermund, A.H.M.; |
Mar 06
IEEE
Xplore |
Content-addressable
memory (CAM) circuits and architectures: a tutorial and survey
|
Pagiamtzis, K.;
Sheikholeslami, A.; |
Mar 06
IEEE
Xplore |
A 600-MS/s 5-bit pipeline A/D converter using digital
reference calibration
|
Varzaghani, A.; Yang, C.-K.K.; |
FEB 06
IEEE
Xplore |
A regulated charge pump
with small ripple voltage and fast start-up
|
Jae-Youl Lee; Sung-Eun
Kim; Seong-Jun Song; Jin-Kyung Kim; Sunyoung Kim; Hoi-Jun
Yoo; |
FEB 06
IEEE
Xplore |
Low-power-consumption direct-conversion CMOS transceiver for
multi-standard 5-GHz wireless LAN systems with channel bandwidths of
5-20 MHz
|
Maeda, T.; Yano, H.; Hori, S.; Matsuno, N.; Yamase, T.;
Tokairin, T.; Walkington, R.; Yoshida, N.; Numata, K.; Yanagisawa,
K.; Takahashi, Y.; Fujii, M.; Hida, H.; |
FEB 06
IEEE
Xplore |
A 1.2-V RF front-end with
on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl
mu/m CMOS
|
Sivonen, P.; Tervaluoto,
J.; Mikkola, N.; Parssinen, A.; |
FEB 06
IEEE
Xplore |
A 10-bit 250-MS/s binary-weighted current-steering DAC
|
Deveugele, J.; Steyaert, M.S.J |
FEB 06
IEEE
Xplore |
| Replica compensated
linear regulators for supply-regulated phase-locked loops |
Alon, E.; Kim, J.;
Pamarti, S.; Chang, K.; Horowitz, M |
FEB 06
IEEE
Xplore |
| Process and temperature compensation in a 7-MHz CMOS clock
oscillator |
Sundaresan, K.; Allen, P.E.; Ayazi, F.; |
FEB 06
IEEE
Xplore |
| A DLL-biased; 14-bit DS
analog-to-digital converter for GSM/GPRS/EDGE handsets |
Klemmer, N.; Hegazi, E.;
|
FEB 06
IEEE
Xplore |
| A 32-mW 320-MHz continuous-time complex delta-sigma ADC for
multi-mode wireless-LAN receivers |
Arias, J.; Kiss, P.; Prodanov, V.; Boccuzzi, V.; Banu, M.;
Bisbal, D.; Pablo, J.S.; Quintanilla, L.; Barbolla, J.; |
FEB
06
IEEE Xplore |
| I/Q mismatch compensation
using adaptive decorrelation in a low-IF receiver in 90-nm CMOS
process |
Elahi, I.; Muhammad, K.;
Balsara, P.T.; |
FEB 06
IEEE
Xplore |
| On-chip test circuit for measuring substrate and line-to-line
coupling noise |
Weize Xu; Friedman, E.G |
FEB 06
IEEE
Xplore |
| A 3.125 Gb/s limit
amplifier in CMOS with 42 dB gain and 1 /spl mu/s offset
compensation |
Crain, E.A.; Perrott,
M.H.; |
FEB 06
IEEE
Xplore |
| Patent Abstracts |
|
FEB 06
IEEE
Xplore |
A 60-GHz CMOS receiver
front-end
|
Razavi, B.; |
JAN 06
IEEE
Xplore |
Overview of the architecture; circuit design; and physical
implementation of a first-generation cell processor
|
Pham, D.C.; Aipperspach, T.; Boerstler, D.; Bolliger, M.;
Chaudhry, R.; Cox, D.; Harvey, P.; Harvey, P.M.; Hofstee, H.P.;
Johns, C.; Kahle, J.; Kameyama, A.; Keaty, J.; Masubuchi, Y.; Pham,
M.; Pille, J.; Posluszny, S.; Riley, M.; Stasiak, D.L.; Suzuoki, M.;
Takahashi, O.; Warnock, J.; Weitzel, S.; Wendel, D.; Yazawa, K.;
|
JAN 06
IEEE
Xplore |
| A 950-MHz rectifier
circuit for sensor network tags with 10-m distance |
Umeda, T.; Yoshida, H.;
Sekine, S.; Fujita, Y.; Suzuki, T.; Otaka, S.; |
JAN 06
IEEE
Xplore |
| A VLSI analog computer/digital computer accelerator |
Cowan, G.E.R.; Melville, R.C.; Tsividis, Y.P.; |
JAN 06
IEEE
Xplore |
| The microarchitecture of
the synergistic processor for a cell processor |
Flachs, B.; Asano, S.;
Dhong, S.H.; Hofstee, H.P.; Gervais, G.; Roy Kim; Le, T.; Peichun
Liu; Leenstra, J.; Liberty, J.; Michael, B.; Hwa-Joon Oh; Mueller,
S.M.; Takahashi, O.; Hatakeyama, A.; Watanabe, Y.; Yano, N.;
Brokenshire, D.A.; Peyravian, M.; Vandung To; Iwata, E.; |
JAN 06
IEEE
Xplore |
Ultra-dynamic Voltage scaling (UDVS) using sub-threshold
operation and local Voltage dithering
|
Calhoun, B.H.; Chandrakasan, A.P.; |
JAN 06
IEEE
Xplore
|
MOS operational amplifier design-a tutorial overview
|
Gray, P.R.; Meyer, R.G.
|
DEC 82
IEEE
Xplore |
