This paper describes design techniques to maximize the efficiency and power density of fully integrated switched-capacitor (SC) DC-DC converters. Circuit design methods are proposed to enable simplified gate drivers while supporting multiple topologies (and hence output voltages). These methods are verified by a proof-of-concept converter prototype implemented in 0.374 mm² of a 32 nm SOI process. The 32-phase interleaved converter can be configured into three topologies to support out... Read More »

Millimeter-wave transmitters designed for dense signal constellations must deal with severe linearity-efficiency trade-offs. This paper proposes a method of blending beamforming and linearization that reduces the number of power amplifiers and avoids the loss of on-chip transformers. Two constant-envelope beams are combined in space to deliver a variable-envelope signal, relaxing the linearity of transmitters. A dual-transmitter prototype fabricated in 65-nm CMOS technology and designed for the ... Read More »

This paper analyzes various aspects of the performance of LC VCOs over temperature with emphasis on the temperature dependence of K_VCO. A novel frequency-tuning scheme is proposed which allows wide temperature range operation while keeping the average K_VCO low. Read More »

This paper presents an efficient energy harvester for RF-powered sensor networks. The circuit is based on an improved multi-stage rectifier, which exploits a fully passive threshold self-compensation scheme to overcome the limitation due to the input dead zone. A CAD-oriented design methodology is also proposed, which is aimed at maximizing the overall power conversion efficiency of the harvester through an optimum trade-off among matching losses, power reflection and rectifier efficiency. Accor... Read More »

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which... Read More »

A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital ... Read More »

A unified receiver front-end (RFE) for mobile TV covering the VHF-III, UHF and L bands is described. Performance, power and area efficiencies are advanced in threefold: 1) a gain-boosting current-balancing balun-LNA exhibits high linearity, wideband output balancing and adequate S₁₁ against gain control; 2) a current-reuse mixer-low-pass-filter merges quadrature-/harmonic-rejection mixing and third-order current-mode post-filtering in one block, enhancing linearity and noise just wher... Read More »

This paper reports a digital phase locked loop (D-PLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed converter achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or voltage conversion range. The D-PLL is programmable over a wide range of parameters and can be synchronized to a clock reference to ensure proper frequency lock and switching operation ... Read More »

This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, base... Read More »

A MOS-input operational amplifier has a reconfigurable input stage that enables trimming of both offset and offset drift based only on single-temperature measurements. The input stage consists of a MOS differential pair, whose offset drift is predicted from offset voltage measurements made at well-defined bias currents. A theoretical motivation for this approach is presented and validated experimentally by characterizing the offset of pairs of discrete MOS transistors as a function of bias curre... Read More »

Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar-derived two-stage architecture. Alternative circuit approaches for optimization of particular perfo... Read More »

This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13- μm 1P4M process with pixel pitch of 2.25 &... Read More »

A direct digital frequency synthesizer (DDFS) using an analog-sine-mapping technique is presented in a 0.35-μm SiGe BiCMOS process. We intend to apply the translinear principle to develop a triangle-to-sine converter (TSC) that can achieve outputs with low harmonic content. The TSC is introduced for the DDFS to translate phase data to sine wave. Using this analog-interpolating technique, the DDFS, with 9 bits of phase resolution and 8 bits of amplitude resolution, can achieve operation at... Read More »

The linearity of conventional active-RC filters is limited by the operational transconductance amplifiers (OTAs) used in the integrators. Transconductance-capacitance (Gm-C) filters are fast and can be linear- however, they are sensitive to parasitic capacitances. We explore the Gm-assisted OTA-RC technique, which is a way of combining Gm-C and active-RC integrators in a manner that enhances the linearity and speed of the latter, while adding negligible extra noise or power dissipation. Measurem... Read More »

Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex. We pro pose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC. The prototype 12b 50 MS/s ADC achieves an ENOB of 10.4b at Nyquist,... Read More »

A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-GHz switching Inverse Class-D power amplifier. Low-power digital filtering on the amplitude path helps remove spectral images for coexistence. The transmitter integrates the complete LO distribution network and digital drivers. Operating from a 1-V supply, the PA has 21.8-dBm peak output power with 44% efficiency. Simple static predistortion helps the transmitter meet EVM and mask requirements of 802.11g... Read More »

This paper proposes a novel programmable vision chip based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit (MPU). The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N × N) parallelism and an O(N) parallelism, respectively. The PE array and RPs ... Read More »

This paper presents a highly integrated and fully balanced signal generation block comprising a fundamental-wave voltage-controlled oscillator (VCO), an output buffer, and a configurable frequency divider stage (prescaler). The VCO introduces a negative resistance structure in conjunction with capacitive cross-coupling. This compound structure allows fundamental oscillation to be sustained at high frequencies while providing wide tuning ranges. The capabilities of the capacitive feedback were an... Read More »

This paper proposes two crosstalk-aware signaling techniques based on pulse width modulation (PWM) for energy-efficient on-chip global busses. Two bits of information are encoded into transition type and pulse width for transmission over one wire. The effect of crosstalk on pulses is compensated by pre-correction techniques and self-calibration circuitry mitigates variability. Measurements from 5 mm on-chip links in 65 nm CMOS show that the proposed schemes simultaneously achieve 15% performance... Read More »

We present an ultra-low voltage, highly linear, low noise integrated CMOS receiver operating from a 0.6-V supply. The receiver incorporates programmable, in-band feed-forward interferer cancellation at the baseband to obtain high linearity and low noise operation at ultra-low supply voltages. Being able to reject adjacent channel or far-out blockers, the digitally calibrated interferer cancellation improves the IIP₃ and IIP₂ by more than 13 dB and 8 dB respectively with ver... Read More »

The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. Read More »

A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances th... Read More »

A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices Read More »

A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power efficient in the presenc... Read More »

A 3.8 Gb/s multi-drop single-ended integrating DFE (IDFE) receiver is implemented in a 0.18 um CMOS by using a single-loop LMS-algorithm to find the DFE coefficients automatically. Initially, a preamble input data pattern ('1101') is applied to the main IDFE circuit to determine the DFE coefficients, while a fixed input data pattern ('1111') is applied to the replica IDFE circuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coeffi... Read More »