IEEE Transactions on Very Large Scale Integration (VLSI) Systems

The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main c... View full abstract»

In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with... View full abstract»

This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading ... View full abstract»

Several state-of-the-art monitoring and control systems, such as dc motor controllers, power line monitoring and protection systems, instrumentation systems, and battery monitors, require direct digitization of high-voltage (HV) input signals. Analog-to-digital converters (ADCs) that can digitize HV signals require high linearity and low-voltage coefficient capacitors. A built-in self-calibration ... View full abstract»

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of... View full abstract»

A 6-bit flash analog-to-digital converter (ADC) using reference-voltage-interpolated calibration to improve linearity and reduce power dissipation is presented. In the ADC, the digital calibration logic employs the successive approximation algorithm and the minimized residue algorithm to determine precise calibration levels. Implemented by a 90-nm CMOS process, the proposed ADC can achieve a signa... View full abstract»

Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration does not directly support the block processing unlike direct-form configuration. In this paper, we explore the possibility of realization of block FIR filter in transpose ... View full abstract»

Current neural networks are accumulating accolades for their performance on a variety of real-world computational tasks including recognition, classification, regression, and prediction, yet there are few scalable architectures that have emerged to address the challenges posed by their computation. This paper introduces Minitaur, an event-driven neural network accelerator, which is designed for lo... View full abstract»

In this transaction brief we consider the design of dual basis inversion circuits for GF(2/sup m/). Two architectures are presented-one bit-serial and one bit-parallel-both of which are based on Fermat's theorem. Finite field inverters based on Fermat's theorem have previously been presented which operate over the normal basis and the polynomial basis. However there are two advantages to be gained... View full abstract»

The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such a... View full abstract»

The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the ... View full abstract»

The power budget is expected to limit the portion of the chip that we can power ON at the upcoming technology nodes. This problem, known as the utilization wall or dark silicon, is becoming increasingly serious. With the introduction of 3-D integrated circuits (ICs), it is likely to become more severe. Thus, how to take advantage of the extra transistors, made available by Moore's law and the onse... View full abstract»

This brief presents the key concept, design strategy, and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architectures that can be configured to operate either for circular or for hyperbolic trajectories in rotation as well as vectoring-modes. It can, therefore, be used to perform all the functions of both circular and hyperbolic CORDIC. We propose three reconfigura... View full abstract»

A leakage current compensation design for nanoscale SRAMs is proposed in this paper. The proposed compensation design is composed of a leakage current sensor, which generates a warning signal if the leakage is over a predefined threshold, and a compensation circuit following the sensor, which will be activated to speed up the read operation. At 0.6 V system voltage, the proposed compensation desig... View full abstract»

A generic statistical model for calculating input-referred noise of an analog-to-digital converter (ADC) impaired by thermal noise is proposed. Based on this model, detailed statistical analyses are performed on three successive approximation register (SAR) ADCs and the analytical results obtained are verified with Monte Carlo simulations. To compare the input-referred noise of different SAR ADC a... View full abstract»

The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current (IW), ON/OFF-state resistance (RON/ROFF), and I-V nonlinearity ratio, interconnect material, and write/read scheme are sys... View full abstract»

This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor (μP) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system ... View full abstract»

There are four main sources of jitter in delay-locked loops (DLLs). In this paper, DLL's jitter due to uncertainties in these sources of jitter is calculated. Time domain equations of DLL are introduced, which are the key parameters to obtain a closed-form equation related to jitter of DLL in the presence of noisy phase-frequency detector, charge pump, delay cells, and reference clock. First, DLL'... View full abstract»

This paper presents the design of a compact 60-GHz phase shifter that provides a 5-bit digital phase control and 360° phase range for beam-forming systems. The phase shifter is designed using the proposed cross-coupled bridged T-type topology and switched-varactor reflective-type topology. The topologies are analyzed using a small-signal equivalent circuit model. Furthermore, the design equ... View full abstract»

This paper presents a 60-GHz power amplifier (PA) fabricated in a 65-nm CMOS technology. The proposed PA utilizes a dual-mode amplification circuit topology to achieve a high level of output power and efficiency in a small die area. High-output power is achieved by combining class AB cascode stage with a conventional class A common source (CS) stage in a compact four-way differential distributed a... View full abstract»

Single-stage regulator topologies are often preferred in embedded applications due to their low power consumption with a single-pole behavior, resulting in easy frequency compensation. Since the achievable differential gain from a single stage is low, the dc load regulation is poor over a wide dynamic range. This paper presents a single-stage, adaptively biased, low-dropout regulator to achieve a ... View full abstract»

In this paper, we analyze the contents of lookup tables (LUTs) of distributed arithmetic (DA)-based block least mean square (BLMS) adaptive filter (ADF) and based on that we propose intra-iteration LUT sharing to reduce its hardware resources, energy consumption, and iteration period. The proposed LUT optimization scheme offers a saving of 60% LUT content for block size 8 and still higher saving f... View full abstract»

When operating at scaled supply voltages, the primary source of performance degradation in a successive approximation register (SAR) analog-to-digital converter (ADC) is the comparator thermal noise. Low-noise comparator can be used but at the expense of increased power dissipation. This paper presents an approach to reduce the comparator power in SAR ADCs. A mathematical model of a SAR ADC derive... View full abstract»

The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection.... View full abstract»

Field-programmable gate array (FPGA) devices boast abundant resources with which custom accelerator components for signal, image, and data processing may be realized; however, realizing high-performance, low-cost accelerators currently demands manual register transfer level design. Software-programmable soft processors have been proposed as a way to reduce this design burden, but they are unable t... View full abstract»

Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid configurable logic block architectures, both nonfracturable and fracturable with varying MUX:LUT logic element ratios are evaluated across two benchmark suites (VT... View full abstract»

Conventional charge-based memory usage in low-power applications is facing major challenges. Some of these challenges are leakage current for static random access memory (SRAM) and dynamic random access memory (DRAM), additional refresh operation for DRAM, and high programming voltage for Flash. In this paper, two emerging resistive random access memory (ReRAM) technologies are investigated, memri... View full abstract»

Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM). This paper presents ... View full abstract»

This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while main... View full abstract»

A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse gene... View full abstract»

A CMOS pulsewidth modulation (PWM) transceiver circuit that exploits the self-referenced edge detection technique is presented. By comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle, area-efficient and high-robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate p... View full abstract»

Conventional active noise cancelling (ANC) headphones often perform well in reducing the low-frequency noise and isolating the high-frequency noise by earmuffs passively. The existing ANC systems often use high-speed digital signal processors to cancel out disturbing noise, which results in high power consumption for a commercial ANC headphone. The contribution of this paper can be classified into... View full abstract»

The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO). This paper presents an ADPLL that possesses a coarse frequency selection function. All DCO frequency transfer curves of the ADPLL have gentle slopes. The ADPLL selects one transfer curve before acquisition. T... View full abstract»

Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent power efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also hard to quickly evaluate the feasibilit... View full abstract»

A low-voltage low-dropout (LDO) regulator that converts an input of 1 V to an output of 0.85-0.5 V, with 90-nm CMOS technology is proposed. A simple symmetric operational transconductance amplifier is used as the error amplifier (EA), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the LDO regulator. In the rail-to-rail output stage of ... View full abstract»

Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent process-induced mismatch of SRAM cells. The proposed circuits improve upon those previously published by reducing the number of bits that vary from trial to trial, and... View full abstract»

Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the... View full abstract»

The appearance of radix-2² was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2² was extended to radix-2k . However, radix-2k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2k feedforward (MDC) ... View full abstract»

A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. It achieves write SNM of 1.4× and 1.28× as that of isoarea 6T and read-decoupled 8T (RD-8T), respectively, at 3... View full abstract»

In 3-D-stacked memory chips, the problem of power supply integrity (PSI) is aggravating due to the additional through-silicon-via resistance and the higher current density in 3-D power delivery network. In particular, for the 3-D phase-change memory (PCM) well known for its high-amplitude programming current, IR-drop violation poses a serious threat that enforces a strict guard band of requesting ... View full abstract»

This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations i... View full abstract»

In recent years, researchers have focused toward reduction in power dissipation and cell size to employ spin-transfer torque (STT) magnetic random-access memories (MRAMs) for embedded applications. Hence, the magnetic tunnel junctions (MTJs) with an optimized structure and magnetic properties are being explored to reduce the switching current. However, the switching current reduction in the MTJs g... View full abstract»

This paper describes a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient trilevel alternate switching capacitive digital-to-analog converter (CDAC). The switching scheme of this CDAC preserves the features of the asymmetric-switching CDAC. By narrowing and smoothing the dynamic variation of DAC voltage, the switching scheme diminishes the dyn... View full abstract»

A complete thermal energy harvesting power supply for implantable pacemakers is presented in this paper. The designed power supply includes an internal startup and does not need any external reference voltage. The startup circuit includes a prestartup charge pump (CP) and a startup boost converter. The prestartup CP consists of an ultralow-voltage oscillator followed by a high-efficiency modified ... View full abstract»

A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed data rates will be introduced. Experimental results show ... View full abstract»

Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are comp... View full abstract»

Optical interconnects for system-in-package applications can be designed for various bit rates. In this paper, an optimization study is conducted to find the optimal parameters for electrooptical links, based on a silicon photonic technology. We focus on the bit rate to achieve highest possible power efficiencies. This paper takes all the elements of an electrooptical link into account: serializat... View full abstract»

We propose an all-digital on-chip time-domain temperature sensor for system-on-a-chip (SoC) thermal management. For on-chip purposes, the proposed temperature sensor achieves energy- and area-efficient and fast thermal monitoring by adopting a digitally controlled oscillator (DCO) with the frequency divider and XNOR gate to generate temperature-dependent pulse. The frequency divider with the fine ... View full abstract»

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyz... View full abstract»

In this paper, we present a novel architecture based on field-programmable gate arrays (FPGAs) for the reconstruction of compressively sensed signal using the orthogonal matching pursuit (OMP) algorithm. We have analyzed the computational complexities and data dependence between different stages of OMP algorithm to design its architecture that provides higher throughput with less area consumption.... View full abstract»